1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device in which data is electrically rewritable and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, an LSI is formed by integrating elements in a two-dimensional plane on a silicon substrate. Generally, dimensions of one element are made smaller (dimensions made finer) to increase storage capacity of memory, but in recent years, making dimensions finer is becoming increasingly more difficult in terms of costs and technology. Technological improvement of photolithography is needed to implement finer dimensions, but costs required for a lithography process are ever on the rise. Moreover, even if finer dimensions are achieved, it is expected that physical limits such as breakdown voltage between elements are reached if, for example, the drive voltage is not scaled. That is, it is highly probable that operations as a device will be harder and harder.
Thus, in recent years, many semiconductor memory devices in which memory cells are three-dimensionally arranged have been proposed to increase the integration degree of memory (Japanese Patent Application Laid-Open No. 2007-266143). A non-volatile semiconductor memory device described in Japanese Patent Application Laid-Open No. 2007-266143 has conductive layers and interlayer insulating layers alternately laminated. The conductive layers are set to be a drain-side selection gate electrode, a word line, or a source-side selection gate electrode and the interlayer insulating layers are set to insulation-separate the conductive layers. Then, a hole is opened to form a columnar semiconductor, a tunnel insulating layer, a charge storage layer, a block insulating layer and the like therein.
However, misalignment may occur in a process in which a conductive layer to be a drain-side selection gate electrode and a source-side selection gate electrode are formed in a line form and then, a hole is opened. The misalignment leads to dispersion of characteristics of the selection gate electrodes. Moreover, resistance of the selection gate electrodes increases because the width of a conductive layer formed in a line form decreases due to the hole.